Open Source Summit + Embedded Linux Conference + OSPOCon 2021

RISC-V is an open standard instruction set architecture which is becoming a popular choice for new hardware designs, ranging from low-key ones primarily targeting IoT to high performance multicore SoC capable of running data centers. And modern times RISC-V SoCs quite often have QSPI flash onboard which makes them perfect candidates to use XIP technology. XIP stands for eXecute In Place – a technology that allows code to be executed directly from flash without copying the code to RAM first.That allows to optimize memory footprint very tightly and thus opens up to really low-power IoT Linux appliances. XIP support for 64-bit RISC-V targets (developed by the author of this talk) has recently been accepted into the mainline, so as a part of this talk we'll present a demo how to run a mainline kernel configured for XIP on a RISC-V board. Another part of the talk will cover extending XIP support for RISC-V to 32-bit and MMU-less systems and the opportunities this will open up, especially in the area of low-key battery-powered RISC-V systems with RAM shortage.