Open Source Summit + Embedded Linux Conference + OSPOCon 2021

In the last 10 years, the GPIO and PINCTRL subsystem matured to support almost every possible handling of Programmable Input/Outputs and more generally multiplexing of multiple functions on single "Pins" or group of "Pins". However, what is a "Pin"? What is a multiplexed "Function"? How programmable I/Os and pin functions are designed on the majority of System-On-Chips? Neil will describe this from the Hardware design Point-Of-View, the constraints and the requirements. Then Neil will explain how this particular subject was handled over the years in the Linux kernel, to finally get to the current GPIO & PINCTRL subsystems, and how it articulates with the Device Tree and other Firmware based protocols.

This talk will explore the future of Linux on RISC-V, an open instruction set (ISA).  I walk through the pieces needed to boot Linux on RISC-V including the Privileged Architecture, SBI, OpenSBI and U-Boot.  I will explore how to run a complete system including binary distributions and how to build from source yourself.  I will look at what Linux-capable "hard" RISC-V SoC's currently exist and those that are on the horizon. I will also talk about how support in Linux for RISC-V is continuing to evolve such as the introduction of KVM RISC-V support and look at RISC-V hardware support that is in the process of being upstreamed. I will describe how to participate in the creation of RISC-V specifications, and how the new RISC-V Platform Specification is trying to standardize boot and runtime requirements.  Google Slides: https://tinyurl.com/rv-linux-21

There are a variety of approaches to leveraging Linux in real-time and safety-critical applications, such as those required for planes, trains, automobiles, and robots. Some approaches utilize tick-less PREEMPT_RT kernels that isolate cores for user-level processes, some introduce user-level or virtualization-based unikernels, some leverage Linux CPU hot-plug features to offload cores to auxiliary runtimes or bare metal applications, and some defer to secondary CPU clusters and run realtime or safety workloads on compute islands as found in heterogeneous SoCs. This technical presentation covers emerging “hypervisor-less virtio” technology and its resultant unifying system architecture for the sharing of resources, such as files, tty, IPC, network interfaces and others, whether between processes, kernels, cores and/or CPU clusters - with Linux as the virtio backend for all the approaches mentioned above. Although this talk goes deep to cover the low-level details and present real-world performance results of important hypervisor-less virtio use cases, it is also broadly relevant to computer scientists and technology leaders who create, deliver, and capture embedded software value using a Linux-first approach to real-time and/or safety-based applications.

RISC-V is the hot and upcoming architecture in the embedded space. While a majority of embedded developers have earned their chops programming for ARM processors (and PowerPC beforehand), many have yet to dip their toes into the growing RISC-V ecosystem. This talk will guide attendees through the RISC-V architecture and some of its ISA extensions and then follow Ahmad's and Rouven's journey in applying their ARM knowledge to porting the barebox bootloader to the RISC-V-powered Beagle-V Starlight, while enjoying the fun and woe of early-revision silicon.